Method of manufacturing SRAM having asymmetric silicide layer

ABSTRACT

The present invention relates to a structure of a static random access memory (SRAM) having an asymmetric silicide layer and a method for manufacturing the same. The method for manufacturing a static random access memory (SRAM) having an asymmetric silicide layer, wherein the SRAM is provided with transfer transistors and actuating transistors, the method including the steps of: preparing a semiconductor substrate provided with a low structure of a predetermined configuration; forming gate electrodes of the transfer transistors and the actuating transistors on the semiconductor substrate with being spaced by a predetermined distance; forming spacers on side walls of the transfer transistors and the actuating transistors; forming the transfer transistors implanting impurities into a portion of the semiconductor substrate between the gate electrodes and source/drains of the actuating transistors; forming a silicide blocking layer on a top of regions of the transfer transistors; and forming a silicide layer on a top of gate electrodes of the actuating transistors and a surface of source/drain electrodes.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a structure of a static randomaccess memory (SRAM) having an asymmetric silicide layer and a methodfor manufacturing the same, and more particularly, to a structure of astatic random access memory (SRAM) having an asymmetric silicide layerand a method for manufacturing the same which are capable of increasingthe cell ratio without changing the size of an actuating transistor oran actuating transistor to form the SRAM.

[0003] 2. Description of the Related Art

[0004] Generally, although an SRAM is inferior in memory capacity to adynamic random access memory (DRAM), it has been widely used in thememory field such as a cash memory of a computer which requires highspeed operation since it operates.

[0005] Typically, the SRAM cell is composed of a flip flop circuitprovided with a pair of actuating transistors and a pair of actuatingtransistors, so that memory information is conserved by the voltagedifference between an input and an output terminal of the flip flop,i.e., electrical charges accumulated in a cell node. Also, since theelectrical charges are constantly compensated from the power source Vccthrough a p-channel metal oxide semiconductor (PMOS) transistor as anactuating transistor or a load resistor, the SDRAM does not require arefresh function, as does a DRAM.

[0006]FIG. 1 is a view showing the circuit of a conventional SRAM cell.Referring to FIG. 1, the circuit of a SRAM cell includes a pair ofactuating transistors 10 provided with a PMOS transistor 12 and ann-channel metal oxide semiconductor (NMOS) transistor 14 being connectedto the terminals of a power supply successively and a pair of actuatingtransistors 20 connecting its source to a gate electrode of theactuating transistor 10 alternately. Here, the source of the transfertransistor 20 is crossed at a common node of the PMOS transistor 12 andthe NMOS transistor 14 of the actuating transistors 10. The terminals ofthe power source are connected to a drain of the PMOS transistor 12 ofthe actuating transistors 10 and a ground terminal is connected to thesource of the NMOS transistor 14. A word line(WL) is connected to gateelectrodes of the actuating transistors 20 and bit lines BL, /BL areconnected to the source.

[0007]FIGS. 2a to 2 c are cross-sectional views illustrating a methodfor manufacturing an SRAM in accordance with a prior art. Referring toFIGS. 2a to 2 c, a conventional method for manufacturing an SRAM willnow be described. Here, methods for manufacturing a PMOS transistor 12as an actuating transistor 10 of an SRAM cell and an NMOS transistor asa transfer transistor 20 as shown in FIG. 1 are explained forsimplicity.

[0008] As shown in FIG. 2a, a device isolation layer 2 is formed on asemiconductor substrate 1 and an n-well 3 and a p-well 4 are formed inthe semiconductor substrate 1, respectively. A gate insulating layer 5and gate electrodes 6 of the transfer transistors 20 and the actuatingtransistor, e.g., the PMOS transistor 12, are sequentially formed on topof the n-well 3 and the p-well 4 of the semiconductor substrate 1. Also,spacers 7 are formed on a side wall of the gate electrodes 6, a p+source/drain 8 of the actuating transistor is formed on the n-well 3 andn+ source/drain 9 of the transfer transistor 20 is formed on the p-well4. Here, each of the source/drains 8, 9 employs a lightly doped drain(LDD) structure.

[0009] Subsequently, as shown in FIG. 2b, a silicide layer 11 is formedon a top of the actuating transistor 12 and the gate electrodes 6 of thetransfer transistor 20 and a surface of the source/drain electrodes 8, 9by performing a salicide process.

[0010] Then, as shown in FIG. 2c, an interlayer insulating layer 13 isformed on an entire surface of the resultant structure formed with thesilicide layer 11, a contact hole is formed in the interlayer insulatinglayer 13 and contact electrodes 15 are formed with a conductive layer toconnect the actuating transistor 12 and the source/drain of the transfertransistor 20.

[0011] After the constructed SRAM cell applies a voltage opposite toeach other to the bit lines BL, /BL to store data in the cell, thetransfer transistor 20 is turned on by applying the driving power to theword line and the voltage of the bit lines BL, /BL is stored at a commonnode of the PMOS and the NMOS of the actuating transistor 12 based onthe status of the transfer transistor. After the bit lines BL, /BL areprecharged with the same voltage to read the data stored at the SRAMcell, the bit lines BL, /BL change into electrical potentials differentform each other due the a valued stored at the actuating transistor 10by applying the driving power to the word line. This result is sensed bya sense amplifier and the difference between the potentials is amplifiedto thereby read the data.

[0012] Conventionally, there is a major parameter called a cell ratio tosecure a stable data maintaining function and a data stability during adata access. If the precharged transfer transistor 20 is turned on toread the data of the SRAM cell, a potential of one of the bit lines BL,/BL is changed, whereby the stability of the data is dependent on theforce of driving a current of the actuating transistor 10. To understandthis effect, the ratio between the current driving forces of theactuating transistor/transfer transistor is defined as a cell ratio, andpreferably is approximately larger than two.

[0013] Whereas, in the SRAM cell, there is a method to increase awidth/length ratio of the transistor so as to increase the cell ratio ina given electron mobility and gate capacitance. A method to reduce thelength for the same width has a limit due to the fixation of a minimumvalue to supply a given processor, therefore, a method to increase thewidth for the same length has been widely used. However, it causes anincrease in the area of the SRAM cell, thereby making a high integrationof the semiconductor device difficult.

SUMMARY OF THE INVENTION

[0014] It is a major object of the present invention to solve the abovementioned problems of the prior art and to provide a structure of astatic random access memory (SRAM) having an asymmetric silicide layerwhich is capable of increasing the cell ratio without increasing thesize of an SRAM cell by reducing the current driving force of a transfertransistor in comparison with that of the actuating transistor, this isachieved by increasing surface resistance of the transfer transistor bynot forming a silicide thereon and decreasing surface resistance of theactuating transistor by forming a silicide thereon.

[0015] It is another object of the present invention to provide to amethod for manufacturing a static random access memory (SRAM) having anasymmetric silicide layer which is capable of increasing a cell ratiowithout increasing the size of an SRAM cell by reducing the currentdriving force of a transfer transistor in comparison with that of theactuating transistor, this is achieved by increasing the surfaceresistance of the transfer transistor by not forming a silicide thereonand decreasing surface resistance of the actuating transistor by forminga silicide thereon.

[0016] In accordance with one aspect of the present invention, there isprovided a structure of a static random access memory (SRAM) having anasymmetric silicide layer, wherein the SRAM is provided with transfertransistors and actuating transistors, the structure including: asemiconductor substrate provided with a substructure of a predeterminedconfiguration; a gate insulating layer and gate electrodes of thetransfer transistors and the actuating transistors formed on thesemiconductor substrate spaced at a predetermined distance; a spacerformed on side walls of the gate electrodes of the transfer transistorsand the actuating transistors, respectively; source/drain electrodes ofthe transfer transistors and the actuating transistors implanted into aportion of the semiconductor substrate placed between the gateelectrodes; a silicide blocking layer formed on the top region of theresultant structure of the transfer transistor; and a silicide layerformed on a top of the gate electrodes of the actuating transistors andsurfaces of the source/drain electrodes.

[0017] Preferably, the silicide blocking layer is made of an oxidematerial.

[0018] Preferably, The widths of the gate electrodes of the transfertransistors are equal to those of the actuating transistors.

[0019] In accordance with another aspect of the present invention, thereis provided a method for manufacturing a static random access memory(SRAM) having an asymmetric silicide layer, wherein the SRAM is providedwith transfer transistors and actuating transistors, the methodincluding the steps of: preparing a semiconductor substrate providedwith a substructure of a predetermined configuration; forming gateelectrodes of the transfer transistors and the actuating transistors onthe semiconductor substrate being spaced at a predetermined distance;forming spacers on side walls of the transfer transistors and theactuating transistors; forming a silicide blocking layer on the topregions of the transfer transistors; and forming the transfertransistors implanting impurities into a portion of the semiconductorsubstrate between the gate electrodes and source/drains of the actuatingtransistors.

BRIEF DESCRIPTION OF DRAWINGS

[0020] Other objects and aspects of the present invention will becomeapparent from the following description of the embodiments withreference to the accompanying drawings in which:

[0021]FIG. 1 is a view showing a conventional circuit of an SRAM cell;

[0022]FIGS. 2a to 2 c are cross-sectional views illustrating a methodfor manufacturing an SRAM in accordance with a prior art; and

[0023]FIGS. 3a to 3 d are cross-sectional views illustrating a methodfor manufacturing an SRAM having an asymmetric silicide layer inaccordance with a preferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] A preferred embodiment of the present invention will now bedescribed with reference to the accompanying drawings. These embodimentsare described by way of example, and therefore these embodiments do notlimit the scope of the present invention. In the following description,same drawing reference numerals are used for the same elements even indifferent drawings.

[0025]FIGS. 3a to 3 d are cross-sectional views illustrating a methodfor manufacturing an SRAM having an asymmetric silicide layer inaccordance with a preferred embodiment of the present invention.Referring to the drawings, the SRAM manufacturing method of the presentinvention is described hereinafter. Here, methods for manufacturing aPMOS transistor 12 as an actuating transistor 10 of an SRAM cell and anNMOS transistor as a transfer transistor 20 as shown in FIG. 1 areexplained for simplicity.

[0026] Primarily, as shown in FIG. 3a, a semiconductor substrate 100provided with a substructure of a predetermined configuration isprepared. Then, n-wells 103, 104 and a p-well (not shown) are formed inthe semiconductor substrate 100. A gate insulating layer 105 and gateelectrodes 106 are sequentially formed on top portions of hesemiconductor substrate 100 formed on the n-wells 103, 104,respectively. At this time, since a width and a length of the gateelectrodes 106 of the transfer transistor 20 are equal to those of theactuating transistor 10, the channel width and length of the transfertransistor are equal to those of the actuating transistor 10. That is,in order to increase the cell ratio of the SRAM cell, the cell ratio canbe increased by increasing a surface resistance of the gate electrodesand the source/drain of the transfer transistor 20 until it is largerthan that of the actuating transistor 10 of the SRAM without the size ofthe transistors.

[0027] Also, spacers 107 are formed on the side walls of the gateelectrodes 106 and n+ source/drain 108 of the transfer transistor 20 isformed on the n-well 103 and n+ source/drain 109 of the actuatingtransistor 20 is formed on the n-well 104. Here, each of thesource/drains 108, 109 may employ a lightly doped drain (LLD) structure.

[0028] Subsequently, as shown in FIG. 3b, a silicon oxide layer isformed on a top portion of the transfer transistor 20 formed on theresultant structure.

[0029] In the next step, as shown in FIG. 3c, a silicide layer 112 isformed on top of the gate electrode 106 of the actuating transistor 10and top surfaces of the source/drain 109 by performing a salicideprocess. At this time, since the silicide blocking layer 110 is formedon a region of the transfer transistor 20, the silicide layer is notformed on top of the gate electrode 106 of the transfer transistor 20and on the top surface of the source/drain 108. Resultantly, since thesilicide layer 112 is formed on the gate electrode 106 of the actuatingtransistor 10 and the source/drain 109, a surface resistance decreases,whereas surface resistance of the gate electrode 106 of the transfertransistor 20 and the source/drain 109 increases.

[0030] Then, as shown in FIG. 3d, an interlayer insulating layer 113 isformed along the entire of the resultant structure, contact holes areformed in the interlayer insulating layer 113 and contact electrodes 114are formed in the contact holes with a conductive material to connectthe source/drains 108, 109 of the actuating transistor 10 and thetransfer transistor 20 to each other.

[0031] Therefore, after the silicide blocking layer 110 is formed on topof the gate electrode 106 and the source/drain 108 of the transfertransistor 20 is formed, the present invention selectively forms thesilicide layer 112 only on the actuating transistor 10, thereby reducingthe surface resistance of the gate electrode 106 and the source/drain109 of the actuating transistor 10 in comparison with those of thetransfer transistor 20. Accordingly, a current driving ability of thepresent invention is reduced by increasing the resistance of thesource/drain 108 of the transfer transistor 20 to larger than that ofthe actuating transistor 10.

[0032] Thus, if the transfer transistor 20 and the actuating transistor10 are manufactured with the same minimum size, in accordance with thepreferred embodiment of the present invention, since the silicide layer112 is formed on the source/drain 109 of the actuating transistor 10 andthe silicide layer 112 is not formed on the source/drain 108 of thetransfer transistor 20, the current driving force of the actuatingtransistor 10 becomes larger than that of the transfer transistor 20 tothereby increase the cell ratio of the SRAM.

[0033] As described above, since the present invention does not form asilicide on the transfer transistor without increasing the size of theSRAM cell, it is capable of increasing the surface resistance of thesource/drain, whereby the actuating transistor is capable of increasingthe cell ratio of the SRAM cell by increasing the current driving forceof the transfer transistor by reducing the surface resistance of thesource/drain by forming the silicide on the actuating transistor.

[0034] Therefore, the present invention has an advantage in that thereliability and yield of products are improved by increasing the cellratio of the SRAM cell, although the size of the SRAM cell is scaleddown in response to the high integration of a semiconductor device.

[0035] While the present invention has been described with respect tothe preferred embodiments, other modifications and variations may bemade without departing from the spirit and scope of the presentinvention as set forth in the following claims.

1-3. (Canceled).
 4. A method for manufacturing a static random accessmemory (SRAM) having an asymmetric silicide layer, wherein the SRAM isprovided with transfer transistors and actuating transistors, the methodcomprising the steps of: preparing a semiconductor substrate providedwith a substructure of a predetermined configuration; forming gateelectrodes of the transfer transistors and the actuating transistors onthe semiconductor substrate spaced at a predetermined distance; formingspacers on side walls of the transfer transistors and the actuatingtransistors; forming the transfer transistors implanting impurities intoa portion of the semiconductor substrate between the gate electrodes andsource/drains of the actuating transistors; forming a silicide blockinglayer on a top of regions of the transfer transistors; and forming asilicide layer on a top of gate electrodes of the actuating transistorsand a surface of source/drain electrodes.
 5. The method of claim 4,wherein the silicide blocking layer is made of an oxide material.
 6. Themethod of claim 4, wherein the gate electrodes of the transfertransistors have a width equal to those of the sate electrodes of theactuating transistors.